1. Field of the Invention
The invention relates in general to a low voltage CMOS (Complementary Metal Oxide Semiconductor) process buffer, and more particularly to a CMOS process tri-state buffer.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional low voltage CMOS process buffer. The buffer 100 includes a biasing device 102 and a switch device 104. The biasing device 102 receives an input signal Vin and controls control signals VG5 and VG6 of transistors T5 and T6 according to the input signal Vin. The biasing device 102 further biases the control signal VG5 to a specific voltage level through transistors T1 to T4, when the input signal Vin has a high voltage level, to make a crossover voltage of a gate oxide layer of the transistor T5 be smaller than a crossover voltage of a gate oxide layer of a low voltage CMOS process transistor. The transistors T5 and T6 bias the voltage level of an output terminal 104a to the voltage levels of a voltage Vo1 and a grounding voltage according to the control signals VG5 and VG6, respectively, and the voltage of the output terminal 104a serves as an output signal Vout. The voltage Vo1 may have, for example, the highest voltage level of the buffer 100. However, the buffer 100 has several drawbacks.
The output terminal 104a of the buffer 100 only has two states including a high voltage level state and a grounding voltage level state. That is, one of the transistors T5 and T6 is driven to turn on and continuously generate a DC current at any time instant. Consequently, the buffer 100 continuously generates the current and thus becomes more power-consumptive. In addition, when the control signal VG5 is to be biased from the highest voltage level to the low voltage level by way of discharge, the dimensions of the transistors T3 and T4 are restricted, and the discharge current for discharging the control signal VG5 is thus restricted because the transistors T3 and T4 on the discharge path have to bias the control signal VG5 together with the transistor T1. Consequently, the voltage level falling time of the control signal VG5 becomes longer such that the switch device 104 tends to generate the malfunction.